#ifndef __ASM_SMP_H
#define __ASM_SMP_H

#ifdef __SMP__
#ifndef ASSEMBLY

#include 
#include 
#include 
#include 

/*
 *	Support definitions for SMP machines following the intel multiprocessing
 *	specification
 */

/*
 *	This tag identifies where the SMP configuration
 *	information is. 
 */
 
#define SMP_MAGIC_IDENT	(('_'<<24)|('P'<<16)|('M'<<8)|'_') PRESENT VARY MPC_LAPIC; DEPENDS NMI VERSION BUS CONSTANT INTEL_MP_FLOATING BUSTYPE_VL FAST SHOULD SHORT MORE MPC_CONFIG_PROCESSOR PARAMETERS BUSTYPE_PCMCIA UNDERSTAND *((VOLATILE MPF_SIGNATURE[4]; MPF_FEATURE3; MPC_CPUFLAG; INTERNAL PENALTY VOLATILE CPU_MODEL_MASK STRUCT HITS. DECAY MPC_DESTAPIC; EISA+PCI * *)(APIC_REG+REG)); WRITES. MP_INTSRC 0 1 X86_MODEL; 2 3 PROCESSORS 4 5 6 ACTIVE_KERNEL_PROCESSOR; 7 8 /* MPC_BUSTYPE[6] CPUINFO_X86 ENTRIES _MP_ MPF_FEATURE4; MEM_BASE); ? CPU_PRESENT_MAP; A BOOT_CPU_ID; DEFAULT TRANSFER MY FOR MAY ACCORDING MPC_OEM[8]; VALUE. SET NOT VOID SUM SENSIBLE }; MPC_SRCBUSIRQ; HOPEFULLY 0) FUNCTIONS CPU_BOOTPROCESSOR FOLLOWED CPU_STEPPING_MASK UNSIGNED NO CHAR MPF_FEATURE5; HOST MPF_LENGTH; MPC_IRQFLAG; *DEV_ID, STARTUP. MPC_OEMCOUNT; MPC_SPEC; NEEDED KERNEL_FLAG, ANSWER). X86_MASK; MP_INT_SMI SMP_INVALIDATE_NEEDED; _ALWAYS_ MPC_SIGNATURE MCA ID); CPU_ENABLED SMP_MESSAGE_IRQ(INT HAVE_CPUID; OF __ATTRIBUTE((PACKED)); MCA+PCI CPU_NUMBER_MAP[NR_CPUS]; { BUSTYPE_MCA NUMBERS VALUE } ON OR (0) MARKER P5 P6 BOARD CPUS. STORE WILLINGNESS TIME MPC_DSTIRQ; COMPUTING BIT7 PROCESSES PG MPC_SRCBUSID; ALL FEELING SMP_FOUND_CONFIG; PROBABLY WITH APIC SYSCALL_COUNT; RIGHT RETURN PENTIUM 20 IMCR|PIC MPC_APICID; SMP_PROCESS_AVAILABLE; 82489DX AN MPC_APICADDR; LONG); AS SEPARATE NOTE SMP_INVALIDATE_RCV(VOID); MPC_DESTAPICLINT; TIMER X86; ROUTINES/DATA MPC_PRODUCTID[12]; MP_BUS GET_APIC_ID(APIC_READ(APIC_ID)); 64] BE CONFIGURATIONS ACROSS INFO MPF_CHECKSUM; THAT BP AND MPC_OEMSIZE; SMP_ALLOC_MEMORY(UNSIGNED MPC_SIGNATURE[4]; (MAKES BY PRIVATE INTEL CASE THE SPECIFICATION SMP_STORE_CPU_INFO(INT POINTER MP_INT_VECTORED RUN. 0X01 MP_IRQDIR_DEFAULT INT SCHEDULE SMP_PROC_IN_LOCK[NR_CPUS]; ALSO VALID DIG MISSES CACHE CONFIG FAKE MP_LINTSRC 0X0F FDIV_BUG; SO RSS, SYSTEM NUMBER MPC_CONFIG_IOAPIC APIC_WRITE(UNSIGNED MPC_SRCBUS; MPC_CHECKSUM; BUSTYPE_EISA SMP_SCAN_CONFIG(UNSIGNED READS WP_WORKS_OK; MPC_BUSID; CHECKSUM INCURS CONTROLS CPU_FAMILY_MASK PT_REGS SHARED VERSIONS APIC_REG YOU MAGIC OTHER MPC_DSTAPIC; TO UPDATE SYSTEMS. PROVIDE. MP_INT_NMI BETWEEN HANDLERS: FEATURE LONG HLT_WORKS_OK; SMP_RESCHEDULE_IRQ(INT